(NAND ROM as gate array) With three inputs abc where a and b are operands and c is Cin, use a 3×8
decoder (assume one-hot word line and abc as address bits, no detailed implementation needed) and an
8 -word × 2-bit NAND ROM (this is the lookup table by the PDN in a pseudo-NMOS logic style) to
implement a full adder, producing S and Cout . Be careful how NAND works (non-selected word needs
to be a "pass" condition).
